1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to forming vias in semiconductor devices.
2. Related Art
In typical semiconductor structures, gate electrodes are formed over semiconductor layers and source/drains are formed adjacent to the gates in the semiconductor layers. In many cases two adjacent gate electrodes are close together and share a source/drain region. Contacting the source/drain region involves forming a via hole through an interlayer dielectric and between the gates to expose the source/drain region. There is a tension between the desirability of placing adjacent gate electrodes close together to optimize usage of the available space and making adjacent gate electrodes far enough apart to reliably accommodate the via between them. One difficulty is aligning the via to the source/drain region between the gate electrodes that are close together. In forming the via hole, the misalignment can result in excessive etching into the sidewall spacer on one of the gate electrodes which can result in reliability problems and altered transistor performance. As critical dimensions continue to scale, this issue becomes more problematic.
Thus, there is a need for a method that provides an improvement in forming vias to source/drain regions in which the via is close to the gate electrode.